mirror of
https://github.com/masonr/yet-another-bench-script.git
synced 2026-11-07 08:22:53 +08:00
add experimental RISC-V support (#97)
This commit is contained in:
@@ -33,7 +33,7 @@ issue if the binaries are out of date and lacking any security-related and/or
|
||||
performance updates - the daily scheduled workflows should pick up new upstream
|
||||
releases automatically.
|
||||
|
||||
Note: ARM and RISC-V compatibility is considered experimental.
|
||||
Note: RISC-V compatibility is considered experimental.
|
||||
|
||||
### Compile Notes (manual builds)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user